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Source text - English Since the subject of the paper is “The Ramp,” let us examine this simplified ideal case. We will ignore diode and FET voltage drops when they are conducting.
When the power switch Q1 is turned on by the control circuit signal “OUT,” the voltage VIN is applied across the primary winding of T1. This results in a voltage VTOUT being induced on the secondary T1, which is applied to pin 1 of LOUT, the output inductor through D1. This voltage is greater than the voltage on the output, VOUT. This results in a current buildup in the output inductor, LOUT.
When Q1 turns off, the voltage on pin 1 of LOUT drops to zero. However, current is drawn through D2 and continues to flow through LOUT, though it decreases in a linear manner.
For this analysis we are setting the design parameters of a forward converter to have an input voltage range from 36 to 57 volts, and power OUT of 100 watts. The output voltage is set at 5.0 volts at a switching frequency of 100 kHz. We want a maximum output ripple voltage of 50 mV.
The inductor LOUT will be sized for a peak-to-peak ripple current of 20 percent. Select the output capacitor to have half the output ripple as a function of the capacitance, and half as a function of the equivalent series resistance (ESR) of the capacitor.
The calculations for the design to meet these requirements yield a transformer turns ratio of 11 to 2, an output inductor of 4.6 μH and an output capacitor of 400 μF with a maximum ESR of 6.25 mΩ.
The gain of the output filter as a function of the frequency can be calculated from this information (see Figure 3).
Translation - Spanish Como el tema del artículo es “La rampa”, examinemos este caso ideal simplificado. Ignoraremos las caídas de voltaje de los diodos y los transistores de efecto de campo (FET) cuando éstos llevan a cabo conducción.
Cuando el conmutador de alimentación Q1 es activado por la señal del circuito de control “OUT”, el voltaje VIN se aplica a través del bobinado principal de T1. Esto tiene como resultado un voltaje VTOUT inducido en el T1 secundario, que se aplica a la patilla 1 de LOUT, el inductor de salida a través de D1. Este voltaje es superior que el voltaje en la salida, VOUT. Esto produce una formación de corriente en el inductor de salida, LOUT.
Cuando Q1 se desactiva, el voltaje en la patilla 1 de LOUT cae a cero. Sin embargo, la corriente sale a través de D2 y continúa fluyendo a través de LOUT, aunque se reduce de un modo lineal.
Para este análisis, vamos a establecer los parámetros de diseño de un transformador directo con un rango de voltaje de entrada de entre 36 a 57 voltios y una SALIDA de potencia de 100 vatios. El voltaje de salida se fija en 5 voltios con una frecuencia de conmutación de 100 kHz. Deseamos un voltaje de rizado de salida máximo de 50 mV.
El inductor LOUT se dimensionará para una corriente de rizado de pico a pico del 20 por ciento. Seleccionaremos un condensador de salida que tenga la mitad de rizado de salida en función de la capacitancia, y la mitad en función de la resistencia serie equivalente (ESR) del condensador.
Los cálculos para que el diseño cumpla estos requisitos producen una relación de vueltas del transformador de 11 a 2, un inductor de salida de 4,6 μH y un condensador de salida de 400 μF con una ESR máxima de 6,25 mΩ.
La ganancia del filtro de salida en función de la frecuencia puede calcularse a partir de esta información (véase la Figura 3).
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